• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
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    • 专利摘要:
    An electronic chip (100) having at least: - an electronic circuit (106) disposed at a front face (104) of a substrate (102); a first protective layer (120) disposed on a rear face (117) of the substrate; - a resistive element (122) disposed on the first protective layer and facing at least a portion (110) of the electronic circuit, mechanically supported by the first protective layer and electrically and / or inductively connected to the electronic circuit ; a second protective layer (126) covering at least the resistive element; and wherein the first protective layer comprises at least one dielectric material exhibiting resistance to chemical etching by at least one chemical etching agent less than or equal to that of a dielectric material of the second protective layer.
    公开号:FR3035267A1
    申请号:FR1553505
    申请日:2015-04-20
    公开日:2016-10-21
    发明作者:Jean Charbonnier；Stephan Borel
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    [0001] TECHNICAL FIELD AND PRIOR ART The invention relates to the field of security and protection of electronic chips, and relates to an electronic chip comprising means protecting the rear face of the microchip and allowing to prevent access to the electronic circuit of the chip from its rear face. The invention applies to any type of electronic chip used in particular in a smart card: mobile phone chip, bank card, health card, identity document, etc. The attacks that can undergo an electronic chip are generally intended to access confidential data stored in the electronic circuit of the chip in order to clone, modify the stored information, impersonate its owner, etc. An electronic chip can be attacked in many ways: chemical, physical, laser, electromagnetic, electrical, etc. The front face of an electronic chip, that is to say the face of the chip at which the electronic circuit is located, is generally protected by multiple means such as a protective layer protecting the chip against Focused ion probe intrusive attacks (FIB or "Focused Ion Beam"), as well as other protections against glitch, electromagnetic, or cryptanalysis, etc. On the other hand, the back of the electronic chip is generally poorly protected. Without means of protection of this rear face, nothing prevents the implementation of a thinning of the substrate of the chip at its rear face, or the realization of electronic or electrical failures with the infrared laser ("glitch "), The silicon (which is the material generally used) of the substrate being transparent to the characteristic wavelengths of the infrared. The access to the electronic circuit of the chip obtained then makes it possible, for example, to read the data by obtaining the encryption key.
    [0002] Generally, only light detectors (photodiodes) formed at the level of the transistors of the circuit protect the chip vis-à-vis laser attacks on the rear face more or less effectively depending on the case (the detection of an attack by these sensors must normally indicate that there has been intrusion into the chip by laser beam, which triggers the erasure of the data contained in the chip). The access to the secret information of the electronic chips is feasible not only by disturbances by laser stimulation but also by the realization of probing type contact pads directly connected inside the electronic circuit, and this thanks to the modification circuit physics by a focused ion probe (FIB beam). Document DE 100 65 339 A1 describes the protection of a rear face of an electronic chip by producing several capacitors at this rear face. In case of alteration of the rear face of the chip associated with an attack, the change in the value of the capacitances is detected and an action, such as faulting of the chip, is then performed. Such protection is however not suitable for protecting the chip against ion beam ablation attacks. Indeed, even with an optimized design, the sensitivity of the capacitors in the rear face is not sufficient because of their very large total surface, and an impairment of these capacities by ion beams is very difficult to detect. Typically, an ion beam etch is performed on an etch window of 50 μm side, an area equal to 2.5 × 10 -3 mm 2. Considering a chip of standard size of surface equal to 4 mrn2, the etching window represents a variation of less than 1/1000 of the surface of the chip. The document US Pat. No. 8,110,894 B2 describes an electronic chip whose front face comprises an inductance which, by inductive coupling through the chip substrate, detects the presence of a conductive ground plane disposed on the rear face of the chip. . An alteration by an attack of this conductive ground plane induces a variation of the inductive coupling between the front and rear faces of the chip, which leads to faulting of the chip.
    [0003] However, this solution offers a limited level of protection because such protection of the rear face of the chip is quite simple and the conductive metal plane is easily copiable. The back faces of these electronic chips therefore require protection that is effective against the various possible attacks. SUMMARY OF THE INVENTION An object of the present invention is to provide an electronic chip whose rear face is effectively protected vis-à-vis various types of attack, particularly vis-à-vis attacks by thinning, by probe ionic focusing or chemical etching of the back side of the chip. For this, the invention proposes an electronic chip comprising at least: an electronic circuit disposed at a front face of a substrate; a first protective layer disposed on a rear face of the substrate; a resistive element disposed on the first protective layer and facing at least a part of the electronic circuit, mechanically supported by the first protective layer and electrically and / or inductively connected to the electronic circuit; a second protective layer covering at least the resistive element; and wherein the first protective layer comprises at least one dielectric material having resistance to chemical etching by at least one chemical etching agent less than or equal to that of a dielectric material of the second protective layer. The rear face of such an electronic chip is thus protected thanks to the resistive element coupled to the two protective layers.
    [0004] If a mechanical thinning or polishing of the rear face of the electronic chip is implemented, this thinning necessarily causes, after the destruction of the second protective layer, that of the resistive element. This destruction of the resistive element then forms an open circuit which is detected by the electronic circuit of the chip which may, for example, fail. If a chemical etching is carried out in order to reach the electronic circuit from the rear face of the chip, the chemical etching agent used to etch the substrate, for example a solution based on KOH and / or TMAH also destroys the two protective layers, and in particular the first protective layer which mechanically supports the resistive element, because of the nature of the material or materials of these protective layers which are also subjected to the etching implemented to etch the substrate. This destruction of the protective layers therefore also causes destruction of the resistive element which is no longer mechanically supported by the first protective layer, this destruction being detected by the electronic circuit of the chip. During such chemical etching, especially from the side walls of the protective layers, the first protective layer is etched chemically even if the second protective layer is more difficult to attack by the etching agent used. Since the dielectric material of the first protective layer has an etching resistance less than or equal to that of the dielectric material of the second protective layer, the first protective layer is etched more rapidly than the second protective layer (or at the same speed when the two layers of protection are of the same nature), which implies that detection of the intrusion or the attack occurs (via the destruction of the resistive element which is no longer supported mechanically) before the resistive element can be reached and modified by this etching from the second protective layer. In addition, the chemical etching of the first protective layer generally results in the removal of at least a portion of the second protective layer. Advantageously, the first protective layer may be thinner, or thinner, than the second protective layer.
    [0005] The resistance to chemical etching can be quantified by the rate of etching, or etching, or dissolution, of the material in μm / min for an aqueous solution or a given chemistry corresponding to the chemical etching agent. This rate can be measured by measuring the thickness of a layer before and after being exposed to the chemical etching agent for a specified period of time. The ratio of the thickness difference measured over time gives the attack speed. Finally, the dielectric material of the protective layers makes the focused ion probe attacks difficult. In fact, when the dielectric material of the protective layers is subjected to an ion beam, these ions accumulate in the dielectric material at the location targeted by the beam, which creates a localized electrical charge which causes an offset of the ion beam. Ablation of the material then becomes very difficult if not impossible because the ion beam deviates and fails to penetrate deeply into the dielectric material to reach the electronic circuit. In addition, even though a high energy ion beam is used to pass through the dielectric material of the protective layers, this ion beam then damages the resistive element, thereby changing its electrical resistance and thereby triggering detection of this layer. attack by the electronic circuit of the chip. The invention therefore proposes an electronic chip comprising, on the rear face, a combination of an active protection structure (the resistive element) and a passive protection structure (the protective layers) while making this protection system totally opaque vis-à-vis an attack of the back side of the chip. The part of the electronic circuit opposite which the resistive element is arranged may be any part of the electronic circuit, and in particular an electrical routing part, or an active zone comprising for example at least one transistor and / or less a memory. At least the dielectric material of the second protective layer may be resistant to mechanical polishing and / or opaque to infrared radiation and / or resistant to focused ion probe attack.
    [0006] The choice of an opaque dielectric material vis-à-vis infrared radiation forms an additional protection against infrared radiation attacks, for example by infrared laser. For example, the term "opaque to infrared radiation" means a material having a transmission coefficient of less than about 20% with respect to infrared radiation. The expression "resistant to a focused ion probe attack" designates, for example, a material whose abrasion rate by the focused ion probe is less than about 0.5 μm / min for a 50 × 50 attack window. .mu.m.sup.2. At least the dielectric material of the second protective layer 10 may have a Young's modulus greater than or equal to about 1 GPa. Such a Young's modulus gives good resistance to mechanical polishing or mechanical thinning. The dielectric material of the first protective layer and / or the dielectric material of the second protective layer may be a polymer. The choice of a polymer for producing the protective layers is advantageous because it makes it easy to produce the protective layers on either side of the resistive element. The first protective layer and / or the second protective layer may further comprise particles of a first material different from the dielectric material of the first protective layer and / or the dielectric material 20 of the second protective layer, and which are distributed throughout the dielectric material of the first protective layer and / or the dielectric material of the second protective layer. Such particles may in particular form additional protection against FIB etching of the protective layer or layers comprising these particles. This protection against an FIB 25 etching can be obtained thanks to the high hardness of the first material of the particles (for example alumina having a Vickers hardness of the order of 1500 kgf.mm -2). , this hardness being for example greater than or equal to 100 kgf.mm-2. The first material may also be such that the particles disturb a laser beam used on the protective layer or layers which comprise these particles.
    [0007] Advantageously, the first material of the particles may be based on silica and / or alumina. In addition, the first material of the particles may be covered with a second material reflective to light and / or electronic and / or ionic radiation, for example a metallic material. This reflective coating makes it possible to further disturb a light (for example laser) and / or an electronic and / or ionic (FIB) beam that would be applied to the dielectric material of the protective layers. These reflective particles are advantageously used for the second protective layer which has a free face forming the rear face of the electronic chip. The second material can be called reflective when it reflects at least 50% of the light and / or electronic and / or ion. The resistive element may comprise at least one conductive track having at least one serpentine pattern and / or several alternating patterns, intermingled, wound or interlaced. Such a configuration of the resistive element makes it possible to make it difficult or even to prevent the realization of a metal bridge or a short circuit between two parts of the resistive element ("bend of wire") in order to access to the part of the rear face are between these two parts of the resistive element without changing the value of the electrical resistance of the resistive element. In general, the pattern of the resistive element can cover as much as possible the first protective layer, and covers, for example, the entire portion of the first protective layer facing the part of the electronic circuit in front of which find the resistive element to better detect an attack on the back of the chip. In addition, the conductive track may have a width of between about 5 μm and 50 μm, and / or portions of the conductive track that are adjacent and parallel to each other may be spaced apart from each other. the other from a distance of between about 5 μm and 50 μm. Such a configuration of the resistive element thus leaves too little space for an attack by a FIB beam without this causing a significant change in the value of the electrical resistance of the resistive element.
    [0008] The electronic chip may further comprise an electrically conductive layer disposed between the rear face of the substrate and the first protective layer. Such an electrically conductive layer forms an additional protective shield with respect to a laser beam and / or other electromagnetic radiation that can be used to drive the back side of the microchip. For the deposition of this electrically conductive layer, the rear face of the substrate may be electrically insulating or rendered electrically insulating by the prior deposition of an electrically insulating layer on this rear face. The electronic chip may furthermore comprise at least two first conductive vias crossing the substrate and electrically connecting the resistive element to the electronic circuit. Alternatively, the electronic chip may further comprise an inductive element disposed at the front face of the substrate and electrically connected to the electronic circuit, and the resistive element may be part of an RLC circuit (ie an electrical circuit having an electrical resistance, an inductance and a capacitance) adapted to be inductively coupled to said inductive element such that a change in a value of inductance of the inductive element induces a modification of a electrical property of the RLC circuit. Thus, the resistive element is connected to the electronic circuit inductively without using conductive vias crossing the substrate.
    [0009] In this case, the inductive element can be integrated in the electronic circuit. In addition, the resistive element can form a coil whose ends are electrically connected to one another. According to an advantageous embodiment, the electrically conductive layer disposed between the rear face of the substrate and the first protective layer can electrically connect the ends of the coil.
    [0010] The electronic chip may further comprise at least one second via and / or a trench crossing the rear face of the substrate and a portion of the thickness of the substrate, and disposed at least opposite the electronic circuit such as a bottom wall. the second via and / or the trench is spaced from the electronic circuit by a non-zero distance. This or these second vias and / or trenches which do not completely pass through the substrate form a mechanical weakening structure in the substrate which confers additional protection with respect to mechanical thinning or a polishing of the chip from its rear face, and vis-à-vis an attack by FIB or chemical etching of the rear face of the chip. Advantageously, the side walls and the bottom wall of the second via and / or the trench may be covered by the electrically conductive layer disposed on the rear face of the substrate. The invention also relates to a method for producing an electronic chip comprising at least the steps of: - producing an electronic circuit at a front face of a substrate; - Making a first protective layer on a rear face of the substrate; - Making a resistive element on the first protective layer and facing at least one active part of the electronic circuit, the resistive element being mechanically supported by the first protective layer and electrically and / or inductively connected the electronic circuit; - Realization of a second protective layer covering at least the resistive element; wherein the first and second protective layers 20 each comprise at least one dielectric material, and wherein a substrate material and the dielectric material are capable of being chemically etched by at least one etching agent. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be better understood on reading the description of exemplary embodiments given purely by way of indication and in no way limiting, with reference to the appended drawings in which: FIG. 1 represents a sectional view of FIG. an electronic chip, object of the present invention, according to a first embodiment; FIG. 2 represents a view from above of the resistive element of the electronic chip, object of the present invention; - Figure 3 shows a sectional view of an electronic chip, object of the present invention, according to a second embodiment; FIGS. 4A to 4N represent the steps of a method for producing an electronic chip, which is also the subject of the present invention. Identical, similar or equivalent parts of the different figures described below bear the same numerical references so as to facilitate the passage from one figure to another.
    [0011] The different parts shown in the figures are not necessarily in a uniform scale, to make the figures more readable. The different possibilities (variants and embodiments) must be understood as not being exclusive of each other and can be combined with one another.
    [0012] DETAILED DESCRIPTION OF PARTICULAR EMBODIMENTS Referring first to FIG. 1, which is a sectional view of an electronic chip 100 according to a first embodiment. The electronic chip 100 comprises a substrate 102, formed for example of a semiconductor material such as silicon, the thickness of which is generally equal to about 180 μm in the case of an electronic chip 100 of a card. chip. The substrate 102 comprises a front face 104 on which an electronic circuit 106 is formed. The electronic circuit 106 is formed in a dielectric layer 108 comprising, for example, SiO 2, and notably comprises an active part 110 formed of electronic components and intended to be protected. possible attacks of the electronic chip 100. The electronic circuit 106 also has peripheral parts here corresponding to contact pads 112 accessible from the front face of the electronic chip 100. The front face of the electronic chip 100 is formed by a passivation layer 114, corresponding for example to an oxide and nitride bilayer such as SiO 2 and SiN, through which openings are formed to access the contact pads 112. A rear face 117 of the substrate 102 is covered by a dielectric layer 118 which comprises for example a semiconductor oxide such as Si0 2, and / or SiN, for example deposited by PECVD (plasma-assisted chemical vapor deposition) and having a thickness of between approximately 1 μm and 5 μm. The electronic chip 100 also comprises means for protecting its rear face. These protection means comprise here: - an electrically conductive layer 119 disposed on the dielectric layer 118, facing at least the active portion 110 of the electronic circuit 106; A first protective layer 120 covering, in particular, the electrically conductive continuous layer 119; a resistive element 122 disposed on the first protective layer 120 and which is electrically connected to the electronic circuit 106 via first conducting vias 124 which pass through the entire thickness of the substrate 102; A second protective layer 126 covering in particular the resistive element 122 and forming the rear face of the electronic chip 100. The side walls of each first conductive via 124 are covered by parts of the dielectric layer 118. An electrically conductive layer 125 covers these portions of the dielectric layer 118 (which thus forms an insulation between this electrically conductive layer 125 and the substrate 102) as well as the bottom wall of each first conductive via 124 to form an electrical connection between the front faces and The electrically conductive layers 119 and 125 are derived from a single layer of electrically conductive material which corresponds, for example, to copper deposited by ECD (electrochemical deposition) with a thickness of between approximately 1 μm and 5 μm, and / or PVD-deposited tungsten (physical vapor deposition) with a thickness between about 100 nm and 800 nm, and / or titanium. The electrically conductive layer 125 has a substantially constant thickness and therefore does not completely fill the volume of the first conducting vias 124. The remainder of the volume 30 of the first conductive vias 124 is here filled by the dielectric material of the first protective layer 120. The electrically conductive layers 119 and 125 are electrically insulated from one another by etching portions of the deposited layer from which layers 119 and 125 are derived (see isolation regions 123 visible in FIG. engraving the layer from which layers 119 and 125).
    [0013] The diameters of the first vias 124 are, for example, of the order of 80 μm. The resistive element 122 is for example formed by an ECD or PVD deposition of copper or aluminum and with a thickness of between about 1 μm and 20 μm, and advantageously between about 1 μm and 10 μm. The resistive element 122 is electrically connected to the electrically conductive layers 125 of the first conductive vias 124 by conductive portions 127, for example based on copper or aluminum, which pass through the first protective layer 120. The thickness (dimension along the axis Z) of the stack formed of the substrate 102, the electronic circuit 106 and the passivation layer 114 is, for example, less than or equal to about 200 μm. The protective layers 120 and 126 comprise a dielectric material, and advantageously correspond to polymer layers. The thicknesses of the protective layers 120 and 126 are for example between about 3 μm and 50 μm. Advantageously, the polymer is chosen from materials having a Young's modulus making it difficult to mechanically thin and / or polish the electronic chip 100 from its rear face, for example between about 1 and 10 GPa. Such a material is advantageously used at least for the second protective layer 126. The materials of the protective layers 120, 126 may have a coefficient of thermal expansion of between about 10 and 100, and may have a glass transition temperature of between about 100 ° C and 200 ° C. In addition, the materials of the protective layers 120, 126 are dielectric materials, which makes it possible to counter the attacks of the electronic chip 100 by FIB beam because of the phenomenon of charge accumulation occurring in such a dielectric material. resulting in an offset of the ion beam and prevents etching of these protective layers 120, 126. The materials of the protective layers 120, 126 are also selected depending on the nature of the substrate material 102, such that an etching agent typically used to chemically etch the substrate 102 also etches the materials of the protective layers 120, 126. These materials are chosen such that that of the first protective layer 120 has a lower chemical etch resistance. or equal to that of the material of the second protective layer 126. Thus, during such a chemical etching, the first protective layer 120 is necessarily etched even if the second protective layer 126 is not completely. The first protective layer 120 is etched more rapidly than the second protective layer 126 (or at the same speed when the two protective layers 120, 126 are of the same type), which implies that a detection of the intrusion or the attack occurs (via the destruction of the resistive element 122 which is no longer mechanically supported) before the resistive element 122 can be reached by the etching of the second protective layer 126. Advantageously, particles, called "fillers", which are typically silica or alumina, are dispersed in the dielectric materials of the protective layers 120, 126. Such particles interfere with etching of the protective layers 120, 126 by FIB beam. . In addition, such particles also disturb a laser beam that would be used in the case of laser attacks of the electronic chip 100. These particles may advantageously be coated with metal, for example tungsten and / or titanium, to better disrupt a Laser chip etching of the electronic chip 100. The diameters of these particles can range from about 1 μm to 15 μm. The percentage of particles in the protective layers 120, 126 can be between 0% (absence of these particles) and about 90%. The dielectric materials of the protective layers 120, 126 are advantageously chosen such that they are opaque to all the infrared and near infrared wavelength light signals, that is to say wavelengths of between approximately 700 nm and 1 mm. Thus, it is impossible for infrared laser beam driving to visualize the electronic circuitry 106 through the silicon of the substrate 102 and the protective layers 120, 126 to aim at the active portion 110 of the electronic circuit 106 relevant to the 'attack. Advantageously, the protective layers 120, 126 are made from different dielectric materials each having complementary properties. For example, the first protective layer 120 may be made with a first polymer that is opaque to infrared laser beams, and the second protective layer 126 may be made with a second polymer having a hardness greater than that of first polymer and which is loaded with "fillers". This first polymer may be silicone-based, for example DF5770 polymer dispensed by Shin-Etsu, and the second polymer may be based on epoxy resin, for example A2023 polymer distributed by Nagase. As a variant, the second protective layer 126 may cover the sides, that is to say the lateral faces, of the electronic chip 100.
    [0014] In general, the dielectric materials of the protective layers 120, 126 may be selected as having one or more of the following properties: silicone-based or epoxy-resin-based polymer; - preferably black, or white or gray appearance; Preferably photosensitive, in particular for the first protective layer 120; - Young's modulus between about 1 GPa to 10 GPa. During the operation of the electronic chip 100, the electronic circuit 106 first measures the value of the electrical resistance of the resistive element 122. If the value of this electrical resistance does not correspond to the expected value, the data is then blocked and the chip 100 is locked (default). Thus, any attack of the electronic chip 100 from its rear face which causes a break or a change in the value of the resistance of the resistive element 122 is detected by the electronic chip 100, and the electronic chip 100 is blocked by to destroy its functionality.
    [0015] FIG. 2 represents a view from above of the resistive element 122. In the main plane of the electronic chip 100 corresponding to the plane (X, Y) in FIGS. 1 and 2, the resistive element 122 corresponds to a track conductive extending between the first two conductive vias 124 having a serpentine pattern, which makes it possible to cover the surface facing at least the active portion 110 of the electronic circuit 106. In the example of FIG. 2, the pattern of the resistive element 122 covers almost the entire surface of the rear face of the electronic chip 100. Advantageously, the width of the conductive track forming the resistive element 122 and the space between two parallel portions of the conductive track (distance referenced "a" in Fig. 2) are between about 5 μm and 50 μm. Thus, a FIB attack, typically carried out on a surface of the electronic chip 100 corresponding to a square of dimensions equal to 50 μm × 50 μm, necessarily gives rise to a significant modification of the electrical resistance of the resistive element 122. Moreover, a space of at least 5 μm between the different portions of the conductive track makes it possible to pass an etching agent between these portions during a possible etching of the rear face of the electronic chip 100, which in this case causes the destruction of the first protective layer 120 and thus also the destruction of the resistive element 122 which is no longer mechanically supported by it.
    [0016] The pattern formed by the resistive element 122 at the rear face of the electronic chip 100 is advantageously chosen such that it is sufficiently dense and complex for a "wire detour", that is to say the realization of a metal bridge or a short-circuit between two parts of the resistive element 122, or the positioning of an equivalent resistance between the first two conductive vias 124, induces a significant variation in the resistance of the resistive element 122 which can be detected. For example, in the case of a resistive element 122 corresponding to a coil formed by a copper conductor track of width equal to 25 μm, of thickness equal to 10 μm, with spaces between the adjacent portions of the conductive track 30 (dimension "a") equal to 25 μm and covering a surface of the chip equal to 2 mm 2, the electrical resistance of this resistive element 122 is equal to about 7 Q. In case of tearing or cutting of the resistive element 122 by a FIB beam, the value of its electrical resistance becomes infinite. The sensitivity of such a resistive element 122 with respect to a mechanical or chemical attack, or by FIB beam, is therefore much better than for other solutions for protecting the rear face of the chip of the prior art. In a variant, the pattern formed by the resistive element 122 may be different from a coil, and may correspond to several alternating, intermingled, wound or interlaced patterns in order to make this "wire bend" operation very complicated. The dielectric material of the first protective layer 120 is advantageously photosensitive so that it can be insulated and then easily developed to form the locations of the conductive portions 127. This dielectric material is for example a vacuum laminated polymer, which makes it possible to fill the space of the first conductive vias 124 not occupied by the dielectric layer 118 and the electrically conductive layer 125.
    [0017] The combination of the resistive element 122 and the protective layers 120, 126 makes it possible to optimize the two protection modes conferred by these two elements. In fact, a chemical or mechanical attack which is the main limit of the protection conferred by a single polymer protective layer, is systematically detected thanks to the damage generated on the resistive element 122. In the case of an attack mechanical of the rear face of the electronic chip 100, it will tear a portion of the resistive element 122 and create an open circuit between the first conductive vias 124 which will be detected by the electronic chip 100. In the case of an attack the backside of the electronic chip 100, the latter will remove the material of the protective layers 120, 126 surrounding the resistive element 122 and 25 will cause a rupture of the resistive element 122 which will likewise be detected by the electronic chip Finally, a conventional FIB attack will be impossible on the materials of the protective layers 120, 126 because they have a high resistance to etching by FIB. thanks to their dielectric character. In addition, the alignment of the FIB is impossible in the case of opaque dielectric materials. The use of a high energy FIB could make it difficult to blind etch but after having passed through the material of the second protective layer 126, the FIB will necessarily damage the resistive element 122 and this attack will also be detected. FIG. 3 represents a sectional view of an electronic chip 100 according to a second embodiment.
    [0018] In this second embodiment, in addition to the first conducting vias 124 which electrically connect the resistive element 122 to the electronic circuit 106, the electronic chip 100 also comprises several second non-emerging vias 128 made from the rear face 117 of the substrate 102 and to through a portion of the thickness of the substrate 102, facing the electronic circuit 106 and in particular the active part 110. The second vias 128 have depths (dimensions along the Z axis) and dimensions in a plane parallel to the faces main 104 and 117 of the substrate 102 (plane (X, Y)), corresponding to the diameters in the case of second vias 128 of substantially circular sections, advantageously different from each other, and for example chosen randomly during their realization. The depths of the second vias 128 are related to the diameters of the second vias 128, and are chosen in particular as a function of the thickness of the substrate 102. The second vias 128 advantageously have diameters of less than about 80 μm and depths of less than about 200 μm. . Furthermore, since, unlike the first conductive vias 124, the second vias 128 pass only a portion of the thickness of the substrate 102, the diameters of the second vias 128 are smaller than those of the first conductive vias 124. The side walls and the bottom walls of the second vias 128 are covered by the dielectric layer 118. The electrically conductive layer 119 here covers the dielectric layer 118 at the side walls and the bottom walls of the vias 128, as well as at a portion of the rear face 117 of the substrate 102, in particular between the second vias 128. The presence of the second vias 128 at the rear face of the electronic chip 100 forms a mechanical weakening structure of the substrate 102 30 to protect the electronic chip 100 against chemical attacks and / or 3035267 18 FIB etching attacks. Indeed, the bottom walls of the second or vias 128 are advantageously close to the electronic circuit 106, for example such that the distance between the electronic circuit 106 of the bottom wall or walls is less than or equal to about 20 μm, or by example between about 10 and 20 μm. Thus, a chemical attack, for example with a solution of hydrofluoric acid and nitric acid or potassium hydroxide, for the purpose of etching the substrate 102 from its rear face 117 will result in premature destruction of the electronic circuit 106 from the rear face due to the chemical solution or solutions that will attack the bottom walls of the second vias 128 and quickly reach the electronic circuit 106. The second vias 128 thus form an additional protection against this type of attack. In addition, in case of FIB etching attack, the presence of second vias 128 is penalizing, which also forms additional protection with respect to this type of attack. Alternatively, the second or second vias 128 may correspond to one or more trenches formed in a portion of the thickness of the substrate 102. According to a variant of the two embodiments described above, the pattern of the resistive element 122 in a plane parallel to the rear face 117 of the substrate 102 may correspond to that of a coil. The electronic chip 100 then also comprises an inductive element such as a second coil disposed at the front face of the electronic chip 100, for example integrated in the electronic circuit 106, this second coil being coupled inductively with that formed by the resistive element 122. The resistive element 122 is made such that it is part of an RLC circuit inductively coupled with said inductive element of the front face. Thus, a modification of an electrical property of the RLC circuit generated by an attack of the electronic chip at its rear face induces a modification of a value of an inductance of the inductive element integrated in the electronic circuit 106 which can therefore detect this attack. In this variant, it is not necessary to make the first vias 124 since the communication between the electronic circuit 106 and the resistive element 122 is done inductively via the inductive element disposed at the front face 30 of the Electronic chip 100. To form the RLC circuit, the resistive element 122 may be made in the form of a coil whose ends are electrically connected to each other for example by the electrically conductive layer 119. According to FIG. another variant embodiment, it is possible that the electronic chip 100 does not include the electrically conductive continuous layer 119.
    [0019] In this case, the means of protection of the rear face of the electronic chip 100 are formed by the protective layers 120, 126, by the resistive element 122, and possibly by the second vias 128. In all the embodiments and variants previously described, it is possible that the electronic chip 100 has means for protecting its front face 10, corresponding for example to the protection means known from the prior art. FIGS. 4A to 4N represent steps of a method for producing the electronic chip 100 previously described in connection with FIG. 1. As represented in FIG. 4A, the electronic circuit 106 is made at the front face of the substrate 102 via the implementation of conventional steps of microelectronics. The electronic circuit 106 is covered by the passivation layer 114 which forms the front face of the electronic chip 100. This front face is secured to a temporary handle 130 formed for example by a silicon substrate, this bonding being for example made between the oxide-based passivation layer 114 and another oxide layer 132 previously formed on the temporary handle 130. Substrate 102 is then thinned from its back face until the assembly formed of substrate 102 and of the electronic circuit 106 has a thickness less than or equal to about 200 μm (Figure 4B). A hard mask 134, comprising for example an oxide, is then made on the rear face of the substrate 102. The first vias 124 are then formed through the hard mask 134 and the substrate 102 by lithography, etching the hard mask material 134 and deep etching the substrate material 102 (Figure 4C). When the electronic chip 100 comprises the second vias 128 as in the example of FIG. 3, the second vias 128 and the first vias 124 can be made simultaneously via the implementation of common lithography and etching steps. Apertures whose dimensions and positioning correspond to those desired for the second vias 128 are thus formed through the hard mask 134. As shown in FIG. 4D, the dielectric layer 118 is then deposited, for example by PECVD or SACVD (chemical vapor phase deposition under sub-atmospheric pressure), as it covers the hard mask 134 disposed on the rear face of the substrate 102, as well as the side walls and the bottom walls of the first vias 124 (and optionally second vias 128). The portions of the dielectric layer 118 deposited on the bottom walls of the first vias 124 are then removed so that electrical contacts can subsequently be made via these first vias 124. The electrically conductive layers 119 and 125 are then realized. for example by carrying out the following steps: depositing a diffusion barrier layer, formed for example of a Ti / TiN bilayer (Ti deposited for example by PVD and TiN deposited for example by MOCVD, or deposit chemical vapor phase organometallic), on the dielectric layer 118 and at the bottom walls of the first vias 124 (and optionally also on the side walls and the bottom walls of the second vias 128); depositing a growth layer, for example copper, on the barrier layer; 20 - lithography of a dry film (positive or negative resin type) so as to define regions of electrical insulation between the layers 119 and 125) and electrolytic growth, for example copper, from the growth layer; - removal of the dry film, then etching portions of the growth layer and the barrier layer at the isolation regions 123 between the layers 119 and 125. The structure obtained at this stage of the process is shown in FIG. 4E . The first protective layer 120 is then deposited, for example by vacuum rolling, over the entire rear face of the previously obtained structure, that is to say on the electrically conductive layers 119 and 3035267 21 125 as well as at the level of the insulating regions 123 between the layers 119 and 125. The material of the first protective layer 120 is deposited such that it fills the first vias 124 (and possibly the second vias 128). Then, the first protective layer 120 is etched (or photo-defined if this layer is based on photosensitive material) to form openings 136 opening on the conductive layer 125 at each of the first vias 124, these openings 136 forming the locations of the conductive portions 127 to be performed later (Figure 4F). As shown in FIG. 4G, the resistive element 122 as well as the conductive portions 127 are then produced for example by the following steps: depositing a diffusion barrier layer, formed for example by a Ti / TiN bilayer, on the first protective layer 120 and in the apertures 136; depositing a growth layer, for example copper, on the barrier layer; - lithography of a dry film whose pattern (that is to say the places where the resin is removed) corresponds to the regions occupied by the resistive element 122 and conductive portions 127) and electrolytic growth, for example copper from the growth layer; - removal of the dry film, then etching portions of the growth layer and the barrier layer at the regions not occupied by the resistive element 122 and the conductive portions 127. The second protective layer 126 is then deposited by For example, by using a spin coating or by rolling, encapsulating the resistive element 122 between the two protective layers 120, 126 (FIG. 4H). The second protective layer 126 also covers the conductive portions 127. as well as some parts of the first protective layer 120. The temporary handle 130 is then removed. For this, the steps below are for example implemented; A temporary support 138 composed for example of polymer is secured to the second protective layer 126 of the chip 100 (FIG. 41); - The temporary handle 130 is then thinned, for example by grinding (Figure 4J), and is completely removed (Figure 4K).
    [0020] The openings 116 are then made through the passivation layer 114, for example by deposition of a lithography mask 140 (FIG. 4L) and etching (FIG. 4M), in order to form accesses to the contact pads 112. Finally, the temporary support 138 is removed (FIG. 4N).
    权利要求:
    Claims (16)
    [0001]
    REVENDICATIONS1. An electronic chip (100) having at least: an electronic circuit (106) disposed at a front face (104) of a substrate (102); a first protective layer (120) disposed on a rear face (117) of the substrate (102); a resistive element (122) disposed on the first protective layer (120) and facing at least a portion (110) of the electronic circuit (106), mechanically supported by the first protective layer (120) and electrically connected and / or inductively to the electronic circuit (106); a second protective layer (126) covering at least the resistive element (122); and wherein the first protective layer (120) comprises at least one dielectric material having resistance to chemical etching by at least one chemical etching agent less than or equal to that of a dielectric material of the second protective layer (126). ).
    [0002]
    An electronic chip (100) according to claim 1, wherein at least the dielectric material of the second protective layer (126) is resistant to mechanical polishing and / or opaque to infrared radiation and / or resistance to a focused ion probe attack.
    [0003]
    An electronic chip (100) according to claim 2, wherein at least the dielectric material of the second protective layer (126) has a Young's modulus greater than or equal to about 1 GPa.
    [0004]
    4. An electronic chip (100) according to one of the preceding claims, wherein the dielectric material of the first protective layer (120) and / or the dielectric material of the second protective layer (126) is a polymer. 3035267 24
    [0005]
    5. Electronic chip (100) according to one of the preceding claims, wherein the first protective layer (120) and / or the second protective layer (126) further comprises particles of a first material different from the dielectric material of the first protective layer (120) and / or the dielectric material of the second protective layer (126), and which are distributed throughout the dielectric material of the first protective layer (120) and / or the dielectric material of the second protective layer (126).
    [0006]
    The electronic chip (100) of claim 5, wherein the first material of the particles is silica and / or alumina based.
    [0007]
    7. An electronic chip (100) according to one of claims 5 or 6, wherein the first material of the particles is covered with a second reflective material vis-à-vis light and / or electronic and / or ionic radiation . 15
    [0008]
    8. An electronic chip (100) according to one of the preceding claims, wherein the resistive element (122) comprises at least one conductive track having at least one serpentine pattern and / or several alternating patterns, interwoven, coiled or interlaced. 20
    [0009]
    9. An electronic chip (100) according to claim 8, wherein the conductive track has a width of between about 5 μm and 50 μm, and / or in which portions of the conductive track that are adjacent and parallel to each other. to the other are spaced from each other by a distance of between about 5μm and 50μm.
    [0010]
    10. An electronic chip (100) according to one of the preceding claims, further comprising an electrically conductive layer (119) disposed between the rear face (117) of the substrate (102) and the first protective layer (120). 3035267 25
    [0011]
    11. Electronic chip (100) according to one of the preceding claims, further comprising at least two first conductive vias (124) passing through the substrate (102) and electrically connecting the resistive element (122) to the electronic circuit (106). 5
    [0012]
    12. The electronic chip (100) according to one of claims 1 to 10, further comprising an inductive element disposed at the front face (104) of the substrate (102) and electrically connected to the electronic circuit (106), and in wherein the resistive element (122) is part of an RLC circuit adapted to be inductively coupled to said inductive element such as a change in a value of inductance of the inductive element induces a modification of an electrical property of the RLC circuit.
    [0013]
    13. The electronic chip (100) of claim 12, wherein the inductive element is integrated with the electronic circuit (106). 15
    [0014]
    14. Electronic chip (100) according to one of claims 12 or 13, wherein the resistive element (122) forms a coil whose ends are electrically connected to one another. 20
    [0015]
    15. Electronic chip (100) according to one of the preceding claims, further comprising at least a second via (128) and / or a trench through the rear face (117) of the substrate (102) and a portion of the thickness. of the substrate (102), and disposed at least opposite the electronic circuit (106) such that a bottom wall of the second via (128) and / or the trench is spaced from the electronic circuit (106) a distance not zero.
    [0016]
    16. A method of producing an electronic chip (100) comprising at least the steps of: - producing an electronic circuit (106) at a front face (104) of a substrate (102); - producing a first protective layer (120) on a rear face (117) of the substrate (102); - producing at least one resistive element (122) on the first protective layer (120) and opposite at least one part (110) of the electronic circuit (106), the resistive element (122) being mechanically supported by the first protective layer (120) and electrically and / or inductively connected to the electronic circuit (106); - Realizing a second protective layer (126) covering at least the resistive element (122); and wherein the first protective layer (120) comprises at least one dielectric material having resistance to chemical etching by at least one chemical etching agent less than or equal to that of a dielectric material of the second protective layer ( 126).
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    同族专利:
    公开号 | 公开日
    US20160307855A1|2016-10-20|
    EP3086368A2|2016-10-26|
    CN106067460B|2020-06-30|
    EP3086368A3|2017-01-04|
    CN106067460A|2016-11-02|
    US9741670B2|2017-08-22|
    FR3035267B1|2018-05-25|
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    法律状态:
    2016-04-28| PLFP| Fee payment|Year of fee payment: 2 |
    2016-10-21| PLSC| Search report ready|Effective date: 20161021 |
    2017-04-28| PLFP| Fee payment|Year of fee payment: 3 |
    2018-04-26| PLFP| Fee payment|Year of fee payment: 4 |
    2019-04-29| PLFP| Fee payment|Year of fee payment: 5 |
    2020-04-30| PLFP| Fee payment|Year of fee payment: 6 |
    2021-04-29| PLFP| Fee payment|Year of fee payment: 7 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1553505A|FR3035267B1|2015-04-20|2015-04-20|ELECTRONIC CHIP COMPRISING A PROTECTED BACK PANEL|
    FR1553505|2015-04-20|FR1553505A| FR3035267B1|2015-04-20|2015-04-20|ELECTRONIC CHIP COMPRISING A PROTECTED BACK PANEL|
    EP16165837.2A| EP3086368A3|2015-04-20|2016-04-18|Electronic chip comprising a protected rear surface|
    US15/131,378| US9741670B2|2015-04-20|2016-04-18|Electronic chip comprising multiple layers for protecting a rear face|
    CN201610249242.3A| CN106067460B|2015-04-20|2016-04-20|Electronic chip comprising a protected rear surface|
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